user_parameters.h

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#ifndef USER_PARAMETERS_H
#define USER_PARAMETERS_H

#include "utils.h"



#ifdef RECOSIM_PART
#include <systemc.h>
#endif

/*****************************************************************************/
/**************************  BEGIN USER SPACE ********************************/

#define ZC702


#ifdef VIRTEX6

        #define CPU_PRUN 435 //435
        #define P_RECONF 150
        #define RECONF_SPEED 400 //400MB/s
        #define CELL_SIZE 162 //40.5*4Byte //Virtex6 !!


        //ZC702 has 13300 slices?
        //global static power is 22mW
        #define P_STATIC_1CELL 0.001654 //1.7uW/slice static FPGA static power

        #define CPU_PSTATIC 24 //we consider CPU has same power in blank and idle mode
        #define CPU_PIDLE 24
        
        
#endif



#ifdef ZC702

        #define CPU_PSTATIC 291 //we consider CPU has same power in blank and idle mode
        #define CPU_PIDLE 291
        #define CPU_PRUN 410 //435


        //#define P_RECONF (2.8*4*5) // x4 if we suppose 400M is 4*dynamic power consumption at 120M x5 for demo
        #define P_RECONF (2*42+28) // 42mW for FARM at 50MHz (x2 pour 100MHz) + 28 of ICAP clock power
        //#define RECONF_SPEED 120 //120MB/s (PCAP)
        #define RECONF_SPEED 400 //We suppose a highspeed reconf, optimized FaRM
        
        #define CELL_SIZE 162 //40.5*4Byte //Virtex6 !! MUST VERIFY FOR ZC702!!!!!!!!


        //ZC702 has 13300 slices?
        //global static power is 48.51mW
        #define P_STATIC_XC7Z020 48.51
        #define N_SLICES_XC7Z020 13300
        //#define P_STATIC_1CELL 0.003647 //3.6uW/slice static FPGA static power
        #define P_STATIC_1CELL (P_STATIC_XC7Z020/N_SLICES_XC7Z020)

        
        //CPU power model
        //power = a * %CPU use + b | with b idle power and a power/%
        //b = 291
        
        #define PM_CPU_STATIC 89.82
        #define PM_CPU_ALPHA 0.0837
        #define PM_CPU_BETA 0.1790
        
        #define PM_CPU_VOLTAGE 1
        #define PM_CPU_CORENUMBER 2
        #define PM_CPU_FREQUENCY 667
        //power equation is P=Pstatic*Vcore*Ncores+alpha*Vcore*Vcore*Ncores*Freq+beta*Vcore*Vcore*Ncoresrunning*Freq
        

#endif




#define NB_SLICES_APPLICATION 4

enum My_Simulation_states { WCET,BCET,RANDOM};
extern My_Simulation_states tasks_execution_time;
#ifdef RECOSIM_PART
extern sc_event TB_lock[NB_SLICES_APPLICATION];
extern sc_semaphore Slice_lock_IN;
extern sc_semaphore Slice_lock_OUT;
extern sc_time application_start_time;
extern int app_is_running;
#endif
extern int current_application_id;

#define MAX_RZ 40
#define MAX_IMPL 40
//definitions for EA3c
extern double cost_result[MAX_RZ][MAX_IMPL];
extern double cost_energy[MAX_RZ][MAX_IMPL];
extern double cost_time[MAX_RZ][MAX_IMPL];
extern double cost_resource[MAX_RZ][MAX_IMPL];

//definitions for EA3deadline

#define STRATEGY_DVFS
#define STRATEGY_BLANK
//#define STRATEGY_STATIC

#ifdef STRATEGY_DVFS
        #define MAX_FREQ_STEPS 3
#else
        #define MAX_FREQ_STEPS 1
#endif
extern double cost_result_d[MAX_RZ][MAX_IMPL][MAX_FREQ_STEPS];
extern double cost_energy_d[MAX_RZ][MAX_IMPL][MAX_FREQ_STEPS];
extern double cost_time_d[MAX_RZ][MAX_IMPL][MAX_FREQ_STEPS];
extern double cost_resource_d[MAX_RZ][MAX_IMPL][MAX_FREQ_STEPS];

extern unsigned int CPU_FREQUENCIES_STEPS[MAX_FREQ_STEPS];
extern unsigned int global_operating_point;
extern double CPU_VOLTAGES_STEPS[MAX_FREQ_STEPS];




//My_Simulation_states tasking_execution_time = WCET;

/**************************  END USER SPACE ********************************/
/***************************************************************************/

#endif