C:/Users/duhem/Desktop/FoRTReSS/FoRTReSS/FoRTReSS/src/simulation.h
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00001 00021 #ifndef SIMULATION_H 00022 #define SIMULATION_H 00023 00024 #include <iostream> 00025 #include <string> 00026 #include <vector> 00027 #include <map> 00028 using namespace std; 00029 00030 #include "hardwareTask.h" 00031 #include "softwareTask.h" 00032 #include "virtualHardwareTask.h" 00033 #include "RZStats.h" 00034 #include "synthesisReport.h" 00035 #include "processor.h" 00036 #include "task.h" 00037 00038 00040 enum AllocationStrategy {NO_OPTIMIZATION, HIGHEST_FRAGMENTATION, HIGHEST_MEMORY_COST, SHORTEST_RUNTIME}; 00041 static const string allocationStrategyName[4] = {"No optimization", "Highest fragmentation", "Highest memory cost", "Shortest runtime"}; 00042 enum ProcessorAllocationStrategy {SOFT_NO_OPTIMIZATION, SOFT_SHORTEST_RUNTIME}; 00043 static const string processorAllocationStrategyName[2] = {"No optimization", "Shortest runtime"}; 00044 00046 enum ImplementationMetric {EXTERNAL_FRAGMENTATION, POWER_CONSUMPTION}; 00047 static const string implementationMetricName[2] = {"External fragmentation", "Power consumption"}; 00048 00050 enum CompressionEvaluation {MEAN_VALUE, LIST, PLANAHEAD}; 00051 00053 enum PartitioningReturnValue {PARTITIONING_SUCCESS, PARTITIONING_USELESS, PARTITIONING_IMPOSSIBLE, PARTITIONING_FAILURE}; 00054 00056 enum PlanAheadVersion {PLANAHEAD_12_X, PLANAHEAD_13_X, PLANAHEAD_14_X}; 00057 static const string planAheadVersionName[3] = {"12.x", "13.x", "14.x"}; 00058 00060 enum BitstreamGeneration {NONE, PLANAHEAD_IMPLEMENTATION, FINAL_PLANAHEAD_VERIFICATION}; 00061 static const string bitstreamGenerationName[3] = {"None", "PlanAhead implementation", "Final PlanAhead verification"}; 00062 00064 static const int FARM_NB_SLICE = 319; 00065 00066 static const string RZ_XML_EXTENSION = ".rrd"; 00067 00068 00069 class Simulation { 00070 00071 private: 00072 00074 // FoRTReSS parameters // 00076 00077 // STEP 0: Environment 00078 static PlanAheadVersion planAheadVersion; 00079 static string planAheadPath; 00080 static bool VERBOSE_MODE; 00081 00082 // STEP 1: RZ determination per task 00083 static bool USE_RZ_SET_DESCRIPTION_FILE; 00084 static string RZ_SET_DESCRIPTION_FILENAME; 00085 static bool ALLOW_NON_RECTANGULAR_RZ; 00086 static double OVERSIZED_RZ_TRIGGER; 00087 static double RESOURCES_MARGIN; 00088 /*static InterfaceControl INTERFACE_CONTROL; 00089 static bool FULL_INTERFACE_USE;*/ 00090 00091 // STEP 2: RZ sort 00092 static double COST_SHAPE_WEIGHT; 00093 static double COST_COMPLIANCE_WEIGHT; 00094 static double COST_INTERNAL_FRAGMENTATION_WEIGHT; 00095 static bool CHECK_RZ_REDUNDANCY; 00096 00097 // STEP 3: RZ selection for simulation 00098 static ImplementationMetric IMPLEMENTATION_METRIC; 00099 static double TRIGGER_FACTOR_UNACCEPTABLE; 00100 static double TRIGGER_FACTOR_OPTIMUM; 00101 static int MINIMUM_DISTANCE_BETWEEN_RZS; 00102 00103 // STEP 4: Allocation 00104 static AllocationStrategy ALLOCATION_STRATEGY; /* Allocation optimization strategy */ 00105 static ProcessorAllocationStrategy PROCESSOR_ALLOCATION_STRATEGY; /* Allocation optimization strategy for processors */ 00106 00107 // STEP 5: PR cost model 00108 static BitstreamGeneration BITSTREAM_GENERATION; /* Bitstream generation for compression estimation */ 00109 static float Tbus; /* Bus period in nanoseconds */ 00110 static float Ticap; /* ICAP period in nanoseconds */ 00111 static float Nburst; /* Burst length */ 00112 static float tburst; /* Time spent on a burst, in cycles of Tbus */ 00113 static float latency; /* Latency to initiate a transaction on the bus, in cycles of Tbus */ 00114 static float fifoDepth; /* FaRM FIFO depth in 32-bit words */ 00115 00116 00118 // Members // 00120 00121 vector<HwTask> hwTasks; /* Task collection */ 00122 vector<SwTask> swTasks; /* SW Task collection */ 00123 vector<VirtualHwTask> virtualHwTasks; /* Virtual tasks created during the partitioning step */ 00124 00125 vector<RZ> RZset; /* Entire RZ set derived from task collection */ 00126 vector<RZ> RZsubset; /* RZsubset built for simulation */ 00127 vector<int> RZsubsetID; /* IDs of each task added to RZsubset */ 00128 00129 vector<Processor> processorSet; /* Entire RZ set derived from task collection */ 00130 vector<Processor> processorSubset; /* RZsubset built for simulation */ 00131 00132 vector<RZStats> RZSimulationStats; /* Statistics from last simulation for RZs */ 00133 vector<RZStats> processorSimulationStats; /* Statistics from last simulation for processors */ 00134 vector<RZStats> firstRZSimulationStats; /* Statistics from last simulation for RZs */ 00135 vector<RZStats> firstProcessorSimulationStats; /* Statistics from last simulation for processors */ 00136 00137 int nbRZInSimulation; /* Current number of RZs in the simulation set */ 00138 int lastRZInSimulationSet; /* Last RZ from global set in simulation subset */ 00139 int minimalExternalFragmentation; /* Minimal achieved external fragmentation */ 00140 int minimalAllocationCost; /* Minimal allocation cost achieved */ 00141 00142 vector<vector<int> > previousRZTaskAssociation; /* Previous RZ/Task association */ 00143 vector<vector<int> > currentRZTaskAssociation; /* Current RZ/Task association */ 00144 vector<vector<int> > bestRZTaskAssociation; /* Best achieved RZ/Task association */ 00145 00146 vector<vector<int> > currentProcessorTaskAssociation; /* Current Processor/Task association */ 00147 vector<vector<int> > bestProcessorTaskAssociation; /* Best achieved Processor/Task association */ 00148 00149 vector<vector<double> > compressedReconfigurationTimes; /* Compressed reconfiguration times */ 00150 vector<vector<double> > preloadReconfigurationTimes; /* Preload configuration times */ 00151 00152 vector<vector<double> > bitstreamSizes; /* Bitstream sizes in kB */ 00153 00154 00155 // Partitioning step attributes 00156 int nbGreedyRZs; /* Number of 'greedy' RZs (hosting every tasks) */ 00157 int nbRZOptimumSet; 00158 int nbRZUnacceptableSet; 00159 vector<HwTask> optimumTaskVector; /* Vector containing optimum tasks */ 00160 vector<HwTask> acceptableTaskVector; /* Vector containing acceptable tasks */ 00161 vector<HwTask> unacceptableTaskVector; /* Vector containing unacceptable tasks */ 00162 00163 vector<int> optimumTaskVectorID; /* Vector containing optimum tasks IDs */ 00164 vector<int> acceptableTaskVectorID; /* Vector containing acceptable tasks IDs */ 00165 vector<int> unacceptableTaskVectorID; /* Vector containing unacceptable tasks IDs */ 00166 00167 // Simulation attributes 00168 int simulationNumber; 00169 int lastValidSimulationID; 00170 string currentSimulationName; 00171 00172 // Directories used to store result files 00173 string logDirectory; 00174 string traceDirectory; 00175 string CSVDirectory; 00176 string UCFDirectory; 00177 string XMLDirectory; 00178 00179 bool finalVerificationReached; 00180 bool backToUnpartitionedSet; 00181 00182 //vector<InterfaceLocation> physicalInterfacesLocation; 00183 00184 map<string, int> physicalInterfacesLocation; 00185 00186 Device* simulationDevice; 00187 00188 00189 public: 00190 Simulation() { 00191 nbRZInSimulation = 0; 00192 minimalExternalFragmentation = 0; 00193 lastRZInSimulationSet = 0; 00194 nbGreedyRZs = 0; 00195 nbRZOptimumSet = 0; 00196 nbRZUnacceptableSet = 0; 00197 lastValidSimulationID = 0; 00198 simulationNumber = 0; 00199 00200 finalVerificationReached = false; 00201 backToUnpartitionedSet = false; 00202 00203 logDirectory = ""; 00204 traceDirectory = ""; 00205 CSVDirectory = ""; 00206 UCFDirectory = ""; 00207 XMLDirectory = ""; 00208 00209 simulationDevice = new Device(); 00210 } 00211 00212 ~Simulation() { 00213 delete simulationDevice; 00214 } 00215 00216 private: 00217 // Helper functions 00218 bool areAllTasksHosted(vector<HwTask> &t); 00219 bool atLeastOneTaskHosted(vector<HwTask> &t, RZ *rz); 00220 int computeExternalFragmentationCost(void); 00221 double computeRZDistance(int rzid); 00222 int computeRZCost(void); 00223 int findEliteSet(void); 00224 void clearAllocation(void); 00225 void printSelectedRZ(void); 00226 int parseResultFile(void); 00227 void printParsedResultFile(void); 00228 int computeCurrentAllocationCost(void); 00229 double computeMemoryCost(void); 00230 void printPRAreaResources(ostream &stream, bool CSVFile); 00231 void editCurrentCSVFile(void); 00232 bool allocationOptimizationPossible(void); 00233 00234 // Flow functions 00235 void searchRZs(void); 00236 int readInputXMLFile(string filename); 00237 int writeOutputXMLFile(string filename); 00238 void sortRZSet(void); 00239 int defineSimulationRZSet(void); 00240 PartitioningReturnValue definePartitionedRZSet(void); 00241 void defineSimulationProcessorSet(void); 00242 void taskAllocation(void); 00243 void RZAllocation(AllocationStrategy); 00244 void firstTaskAllocation(void); 00245 void firstRZAllocation(void); 00246 void firstProcessorAllocation(void); 00247 void processorAllocation(ProcessorAllocationStrategy); 00248 void printAllocation(void); 00249 void writeTaskAllocation(void); 00250 void computeReconfigurationTimes(void); 00251 int writeRZConfigurationFile(string filename); 00252 int launchSimulation(void); 00253 void generateConstraints(bool); 00254 void renameValidSimulationFiles(bool); 00255 void renameFile(string oldfile, string newfile); 00256 00257 public: 00258 // Main function 00259 void setHwTaskVector(vector<HwTask> &vec); 00260 void setSwTaskVector(vector<SwTask> &vec); 00261 void setProcessorVector(vector<Processor> &vec); 00262 void setInterfaceVector(vector<InterfaceLocation> &vec); 00263 int launchArchGenFlow(void); 00264 void displayParameters(void); 00265 void setLogDirectory(string dir); 00266 void setTraceDirectory(string dir); 00267 void setCSVDirectory(string dir); 00268 void setUCFDirectory(string dir); 00269 void setXMLDirectory(string dir); 00270 00271 void setAllowRectangularRZ(bool val); 00272 void setResourcessMargin(double val); 00273 void setCostShapeWeight(double val); 00274 void setCostComplianceWeight(double val); 00275 void setCheckRZRedundancy(bool val); 00276 void setImplementationMetric(ImplementationMetric val); 00277 void setTriggerFactorUnacceptable(double val); 00278 void setTriggerFactorOptimum(double val); 00279 void setAllocationStrategy(AllocationStrategy val); 00280 void setProcessorAllocationStrategy(ProcessorAllocationStrategy val); 00281 void setBitstreamGeneration(BitstreamGeneration val); 00282 void setTbus(float val); 00283 void setTicap(float val); 00284 void setNburst(float val); 00285 void setTburst(float val); 00286 void setLatency(float val); 00287 void setFIFODepth(float val); 00288 00289 }; 00290 00291 #endif
