zynq_design_1_processing_system7_0_0_sim_netlist.vhdl,vhdl,xil_defaultlib,/media/userdev/DISK_1/DEV_ENSEIGNEMENTS/linux_embarque/2022_2/TMP_DEV/linuxzynq_vivado_proj/project_1/project_1.gen/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_0/zynq_design_1_processing_system7_0_0_sim_netlist.vhdl,incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ee60/hdl"
zynq_design_1_axi_gpio_0_0.vhd,vhdl,xil_defaultlib,../../../bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/sim/zynq_design_1_axi_gpio_0_0.vhd,incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ee60/hdl"
zynq_design_1_rst_ps7_0_100M_0.vhd,vhdl,xil_defaultlib,../../../bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/sim/zynq_design_1_rst_ps7_0_100M_0.vhd,incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ee60/hdl"
zynq_design_1_auto_pc_0_sim_netlist.vhdl,vhdl,xil_defaultlib,/media/userdev/DISK_1/DEV_ENSEIGNEMENTS/linux_embarque/2022_2/TMP_DEV/linuxzynq_vivado_proj/project_1/project_1.gen/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_sim_netlist.vhdl,incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ee60/hdl"
zynq_design_1.vhd,vhdl,xil_defaultlib,../../../bd/zynq_design_1/sim/zynq_design_1.vhd,incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ec67/hdl"incdir="../../../../project_1.gen/sources_1/bd/zynq_design_1/ipshared/ee60/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
