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#include "zynq_design_1_processing_system7_0_0_sc.h"

#include "processing_system7_v5_5_tlm.h"

#include <map>
#include <string>

zynq_design_1_processing_system7_0_0_sc::zynq_design_1_processing_system7_0_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
{
  // configure connectivity manager
  xsc::utils::xsc_sim_manager::addInstance("zynq_design_1_processing_system7_0_0", this);

  // initialize module
    xsc::common_cpp::properties model_param_props;
    model_param_props.addLong("C_EN_EMIO_PJTAG", "0");
    model_param_props.addLong("C_EN_EMIO_ENET0", "0");
    model_param_props.addLong("C_EN_EMIO_ENET1", "0");
    model_param_props.addLong("C_EN_EMIO_TRACE", "0");
    model_param_props.addLong("C_INCLUDE_TRACE_BUFFER", "0");
    model_param_props.addLong("C_TRACE_BUFFER_FIFO_SIZE", "128");
    model_param_props.addLong("USE_TRACE_DATA_EDGE_DETECTOR", "0");
    model_param_props.addLong("C_TRACE_PIPELINE_WIDTH", "8");
    model_param_props.addLong("C_TRACE_BUFFER_CLOCK_DELAY", "12");
    model_param_props.addLong("C_EMIO_GPIO_WIDTH", "64");
    model_param_props.addLong("C_INCLUDE_ACP_TRANS_CHECK", "0");
    model_param_props.addLong("C_USE_DEFAULT_ACP_USER_VAL", "0");
    model_param_props.addLong("C_S_AXI_ACP_ARUSER_VAL", "31");
    model_param_props.addLong("C_S_AXI_ACP_AWUSER_VAL", "31");
    model_param_props.addLong("C_M_AXI_GP0_ID_WIDTH", "12");
    model_param_props.addLong("C_M_AXI_GP0_ENABLE_STATIC_REMAP", "0");
    model_param_props.addLong("C_M_AXI_GP1_ID_WIDTH", "12");
    model_param_props.addLong("C_M_AXI_GP1_ENABLE_STATIC_REMAP", "0");
    model_param_props.addLong("C_S_AXI_GP0_ID_WIDTH", "6");
    model_param_props.addLong("C_S_AXI_GP1_ID_WIDTH", "6");
    model_param_props.addLong("C_S_AXI_ACP_ID_WIDTH", "3");
    model_param_props.addLong("C_S_AXI_HP0_ID_WIDTH", "6");
    model_param_props.addLong("C_S_AXI_HP0_DATA_WIDTH", "64");
    model_param_props.addLong("C_S_AXI_HP1_ID_WIDTH", "6");
    model_param_props.addLong("C_S_AXI_HP1_DATA_WIDTH", "64");
    model_param_props.addLong("C_S_AXI_HP2_ID_WIDTH", "6");
    model_param_props.addLong("C_S_AXI_HP2_DATA_WIDTH", "64");
    model_param_props.addLong("C_S_AXI_HP3_ID_WIDTH", "6");
    model_param_props.addLong("C_S_AXI_HP3_DATA_WIDTH", "64");
    model_param_props.addLong("C_M_AXI_GP0_THREAD_ID_WIDTH", "12");
    model_param_props.addLong("C_M_AXI_GP1_THREAD_ID_WIDTH", "12");
    model_param_props.addLong("C_NUM_F2P_INTR_INPUTS", "1");
    model_param_props.addLong("C_DQ_WIDTH", "32");
    model_param_props.addLong("C_DQS_WIDTH", "4");
    model_param_props.addLong("C_DM_WIDTH", "4");
    model_param_props.addLong("C_MIO_PRIMITIVE", "54");
    model_param_props.addLong("C_TRACE_INTERNAL_WIDTH", "2");
    model_param_props.addLong("C_USE_AXI_NONSECURE", "0");
    model_param_props.addLong("C_USE_M_AXI_GP0", "1");
    model_param_props.addLong("C_USE_M_AXI_GP1", "0");
    model_param_props.addLong("C_USE_S_AXI_GP0", "0");
    model_param_props.addLong("C_USE_S_AXI_GP1", "0");
    model_param_props.addLong("C_USE_S_AXI_HP0", "0");
    model_param_props.addLong("C_USE_S_AXI_HP1", "0");
    model_param_props.addLong("C_USE_S_AXI_HP2", "0");
    model_param_props.addLong("C_USE_S_AXI_HP3", "0");
    model_param_props.addLong("C_USE_S_AXI_ACP", "0");
    model_param_props.addLong("C_GP0_EN_MODIFIABLE_TXN", "1");
    model_param_props.addLong("C_GP1_EN_MODIFIABLE_TXN", "1");
    model_param_props.addString("C_IRQ_F2P_MODE", "DIRECT");
    model_param_props.addString("C_PS7_SI_REV", "PRODUCTION");
    model_param_props.addString("C_FCLK_CLK0_BUF", "TRUE");
    model_param_props.addString("C_FCLK_CLK1_BUF", "FALSE");
    model_param_props.addString("C_FCLK_CLK2_BUF", "FALSE");
    model_param_props.addString("C_FCLK_CLK3_BUF", "FALSE");
    model_param_props.addString("C_PACKAGE_NAME", "clg484");
    model_param_props.addString("COMPONENT_NAME", "zynq_design_1_processing_system7_0_0");

  mp_impl = new processing_system7_v5_5_tlm("inst", model_param_props);

  // initialize AXI sockets
  M_AXI_GP0_rd_socket = mp_impl->M_AXI_GP0_rd_socket;
  M_AXI_GP0_wr_socket = mp_impl->M_AXI_GP0_wr_socket;
}

zynq_design_1_processing_system7_0_0_sc::~zynq_design_1_processing_system7_0_0_sc()
{
  xsc::utils::xsc_sim_manager::clean();

  delete mp_impl;
}

