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# Release Notes for STM32F4xx CMSIS Copyright 2015 STMicroelectronics
## Update History ### V2.4.0 / 14-August-2015 Main Changes Add support of STM32F469xx and STM32F479xx devices Add "stm32f469xx.h" and "stm32f479xx.h" files Add startup files "startup_stm32f469xx.s" and "startup_stm32f479xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains Add Linker files "stm32f469 xx_flash.icf", "stm32f469xx_sram.icf", "stm32f479 xx_flash.icf" and "stm32f479xx_sram.icf" used within EWARM Workspaces Add support of STM32F410xx devices Add "stm32f410cx.h", "stm32f410tx.h" and "stm32f410rx.h" files Add startup files "startup_stm32f410cx.s", "startup_stm32f410rx.s" and "startup_stm32f410tx.s" for EWARM, MDK-ARM and SW4STM32 toolchains Add Linker files "stm32f410cx_flash.icf", "stm32f410cx_sram.icf", "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", "stm32f410tx_flash.icf", and "stm32f410rx_sram.icf" used within EWARM Workspaces ### V2.3.2 / 26-June-2015 Main Changes "stm32f405xx.h", "stm32f407xx.h", "stm32f415xx.h" and "stm32f417xx.h" Update FSMC_BTRx_DATAST and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits "stm32f427xx.h", "stm32f437xx.h", "stm32f429xx.h" and "stm32f439xx.h" Update the defined mask value for SAI_xSR_FLVL_2 "stm32f415xx.h", "stm32f417xx.h", "stm32f437xx.h" and "stm32f439xx.h" HASH alignement with bits namming used in documentation Rename HASH_IMR_DINIM to HASH_IMR_DINIE Rename HASH_IMR_DCIM to HASH_IMR_DCIE Rename HASH_STR_NBW to HASH_STR_NBW system_stm32f4xx.c Remove __IO on constant table declaration Implement workaround to cover RCC limitation regarding peripheral enable dela y SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used ### V2.3.1 / 03-April-2015 Main Changes Header file for all STM32 devices Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF ### V2.3.0 / 02-March-2015 Main Changes Add support of STM32F446xx devices Add "stm32f446xx.h" file Add startup file "startup_stm32f446xx.s" for EWARM, MDK-ARM and TrueSTUDIO toolchains Add Linker files "stm32f446xx_flash.icf" and "stm32f446xx_sram.icf" used within EWARM Workspaces Header file for all STM32 devices Add missing bits definition in the EXTI IMR, EMR, RTSR, FTSR, SWIER and PR registers Update RCC_AHB1RSTR_OTGHRST bit definition Update PWR_CR_VOS bits definition for STM32F40xx and STM32F41xx devices update SAI_xCR1_MCKDIV bit definition ### V2.2.0 / 15-December-2014 Main Changes stm32f4xx.h Add new constant definition STM32F4 system_stm32f4xx.c Fix SDRAM configuration in SystemInit_ExtMemCtl(): change RowBitsNumber from 11 to 12 (for MT48LC4M32B2 available on STM324x9I_EVAL board) Header file for all STM32 devices Add missing bits definition for CAN, FMC and USB peripherals GPIO_TypeDef: change the BSRR register definition, the two 16-bits definition BSRRH and BSRRL are merged in a single 32-bits definition BSRR ### V2.1.0 / 19-June-2014 Main Changes Add support of STM32F411xExx devices Add "stm32f411xe.h" file Add startup file "startup_stm32f411xx.s" for EWARM, MDK-ARM and TrueSTUDIO toolchains All header files Add missing defines for GPIO LCKR Register Add defines for memories base and end addresses: FLASH, SRAM, BKPSRAM and CCMRAM. Add the following aliases for IRQ number and handler definition to ensure compatibility across the product lines of STM32F4 Series; example for STM32F405xx.h #define FMC_IRQn FSMC_IRQn #define FMC_IRQHandler FSMC_IRQHandler and for STM32F427xx.h #define FSMC_IRQn FMC_IRQn #define FSMC_IRQHandler FMC_IRQHandler "stm32f401xc.h" and "stm32f401xe.h": update to be in line with latest version of the Reference manual Remove RNG registers structures and the corresponding bit definitions Remove any occurrence to RNG (clock enable, clock reset,…) Add the following bit definition for PWR CR register #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) #define PWR_CR_LPLVDS ((uint32_t)0x00000400) #define PWR_CR_MRLVDS ((uint32_t)0x00000800) "stm32f427xx.h", "stm32f437xx.h", "stm32f429xx.h" and "stm32f439xx.h" Add a new legacy bit definition for PWR to be in line with latest version of the Reference manual #define PWR_CR_LPUDS PWR_CR_LPLVDS #define PWR_CR_MRUDS PWR_CR_MRLVDS Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version system_stm32f4xx.c Remove dependency vs. the HAL, to allow using this file without the need to have the HAL drivers Include stm32f4xx.h instead of stm32f4xx_hal.h Add definition of HSE_VALUE and HSI_VALUE, if they are not yet defined in the compilation scope (these values are defined in stm32f4xx_hal_conf). Use “__IO const” instead of “__I”, to avoid any compilation issue when __cplusplus switch is defined ### V2.0.0 / 18-February-2014 Main Changes Update based on STM32Cube specification This version and later has to be used only with STM32CubeF4 based development ### V1.3.0 / 08-November-2013 Main Changes Add support of STM32F401xExx devices Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and Ride toolchains: Add SPI4 interrupt handler entry in the vector table ### V1.2.1 / 19-September-2013 Main Changes system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation) Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s" for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose ### V1.2.0 / 11-September-2013 Main Changes Add support of STM32F429/439xx and STM32F401xCxx devices Update definition of STM32F427/437xx devices : extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D stm32f4xx.h Add the following device defines : "#define STM32F40_41xxx" for all STM32405/415/407/417xx devices "#define STM32F427_437xx" for all STM32F427/437xx devices "#define STM32F429_439xx" for all STM32F429/439xx devices "#define STM32F401xx" for all STM32F401xx devices Maintain the old device define for legacy purpose Update IRQ handler enumeration structure to support all STM32F4xx Family devices. Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain the old name for startup files for legacy purpose system_stm32f4xx.c Update the system configuration to support all STM32F4xx Family devices. ### V1.1.0 / 11-January-2013 Main Changes Official release for STM32F427x/437x devices. stm32f4xx.h Update product define: replace "#define STM32F4XX" by "#define STM32F40XX" for STM32F40x/41x devices Add new product define: "#define STM32F427X" for STM32F427x/437x devices. Add new startup files "startup_stm32f427x.s" for all toolchains rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all toolchains system_stm32f4xx.c Prefetch Buffer enabled Add reference to STM32F427x/437x devices and STM324x7I_EVAL board SystemInit_ExtMemCtl() function Add configuration of missing FSMC address and data lines Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing values ### V1.0.2 / 05-March-2012 Main Changes All source files: license disclaimer text update and add link to the License file on ST Internet. ### V1.0.1 / 28-December-2011 Main Changes All source files: update disclaimer to add reference to the new license agreement stm32f4xx.h Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST ### V1.0.0 / 30-September-2011 Main Changes First official release for STM32F40x/41x devices Add startup file for TASKING toolchain system_stm32f4xx.c: driver's comments update ### V1.0.0RC2 / 26-September-2011 Main Changes Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices stm32f4xx.h Add define for Cortex-M4 revision __CM4_REV Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000 Correct some bits definition to be in line with naming used in the Reference Manual (RM0090) GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP PWR_CR_PMODE changed to PWR_CR_VOS PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY Add new define RCC_AHB1ENR_CCMDATARAMEN Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28 system_stm32f4xx.c SystemInit(): add code to enable the FPU SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS SystemInit_ExtMemCtl(): remove commented values startup (for all compilers) Delete code used to enable the FPU (moved to system_stm32f4xx.c file) File’s header updated ### V1.0.0RC1 / 25-August-2011 Main Changes Official version (V1.0.0) Release Candidate1 for STM32F4xx devices ## License Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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